Minimal Instruction Set FPGA AES processor using Handel - C

Abstract

This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISCs architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISCs simplicity, it can be further extended to data encryption systems for certain applications like wireless sensor networks and other low complexity systems which may have severely constrained physical memory requirements. With the availability of the FPGA technology, aids practical implementation of the data encryption purpose processor.